1. Field of the Invention
The invention relates to a fabrication method of a bipolar junction transistor (BJT), and more particularly, to a fabrication method which can effectively reduce the manufacture procedure of a bipolar complementary metal oxide semiconductor (BiCMOS) transistor.
2. Description of the Prior Art
A bipolar junction transistor (BJT) is one of the most important semiconductor devices in modern times. The BJT is a three-terminal device that comprises two inseparable PN junctions. The terminals are called emitter, base, and collector. The BJT device conducts current with electrons and holes simultaneously and has the advantages of high speed and large current allowance in a small device, making the BiCMOS structure comprised of the BJT and CMOS devices popularly used to enhance operational speed. However, the conventional manufacturing procedure of the BiCMOS uses many photo processes to combine the standard BJT and CMOS devices, causing the manufacturing procedure to be very complicated.
Please refer to FIG. 1, which is a cross-sectional diagram of a NPN type BJT on a semiconductor wafer 100 according to the prior art. As FIG. 1 shows, a P type first doping region 104, an N type second doping region 106, and a plurality of isolated structures 108 are formed on a substrate 102. The second doping region 106 is used for defining position of the collector electrode of the BJT, and the isolated structures 108 define at least one predetermined region on the surface of the second doping region 106 for a base electrode region of the BJT. Next, an ion implantation process is performed to form a P type third doping region 110 in the second doping region 106 to form the base electrode of the BJT. A shielding layer 112 is then formed on the surface of the semiconductor wafer 100 to protect the CMOS transistor or other elements on the semiconductor wafer 100. An opening can be formed within the shielding layer 112, an N type doping layer 114 can be formed on the third doping region 110, and portions of the shielding layer 112 are removed. The doping layer 114 is used for the emitter electrode of the BJT, and can be made from epitaxy, amorphous silicon, or polysilicon. For reducing the resistance of the doping layer 114, the doping layer 114 can further include an N type heavy doping. Then, a spacer 116 is formed on the sidewall of the doping layer 114, and a self-aligned silicidation (salicide) process is utilized to form a silicide layer 118 on surfaces of the first doping region 104, the second doping region 106, the third doping region 110 and the doping layer 114. The silicide layer functions as contact regions of the BJT device.
The conventional BiCMOS has a high operational speed, but the manufacturing procedure is too complicated to lower the manufacturing cost. For the cost benefit, many factory owners would rather use other low-speed devices than use the high-speed BiCMOS device.